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250 ksps, 6-channel, simultaneous sampling, bipolar 16-/14-/12-bit adc preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features six independent adcs true bipolar analog inputs pin-/software-selectable ranges: 10 v, 5 v fast throughput rate: 250 ksps i cmos tm process technology low power tbd mw at 250 ksps with 5 v supplies wide input bandwidth tbd db snr at 50 khz input frequency on-chip reference and reference buffers parallel, serial, and daisy-chain interface modes high speed serial interface spi?-/qspi?-/microwire?-/dsp-compatible standby mode: 100 w max 64-lead lqfp applications power line monitoring systems instrumentation and control systems multi-axis positioning systems functional block diagram buf agnd dgnd v 1 cs av cc sclk d out b output drivers control logic t/h v drive ser/par v dd ref v ss t/h t/h t/h t/h t/h v 2 v 3 v 4 v 5 v 6 data/ control lines output drivers d out c output drivers output drivers clk osc convsta convstb convstc dv cc rd buf buf d out a stby wr 16/14/12-bit sar 16/14/12-bit sar 16/14/12-bit sar 16/14/12-bit sar 16/14/12-bit sar 16/14/12-bit sar ad7656-1/ad7657-1/ad7658-1 figure 1. general description the ad7656-1/ad7657-1/ad7658-1 1 contain six 16-/14-/12- bit, fast, low power, successive approximation adcs all in the one package that is designed on the i cmos process (industrial cmos). i cmos is a process combining high voltage silicon with submicron cmos and complementary bipolar technologies. it enables the development of a wide range of high performance analog ics, capable of 33 v operation in a footprint that no previous generation of high voltage parts could achieve. unlike analog ics using conventional cmos processes, i cmos components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size. the ad7656-1/ad7657-1/ad7658-1 feature throughput rates up to 250 ksps. the parts contain low noise, wide bandwidth, track-and-hold amplifiers that can handle input frequencies up to 12 mhz. the conversion process and data acquisition are controlled using convst signals and an internal oscillator. three convst pins allow independent, simultaneous sampling of the three adc pairs. the ad7656-1/ad7657-1/ad7658-1 all have a high speed parallel and serial interface, allowing the devices to interface with microprocessors or dsps. in serial interface mode, the parts have a daisy-chain feature that allows multiple adcs to connect to a single serial interface. the ad7656-1/ ad7657-1/ad7658-1 can accommodate true bipolar input signals in the 4 v ref range and 2 v ref range. the ad7656-1/ ad7657-1/ad7658-1 also contain an on-chip 2.5 v reference. product highlights 1. six 16-/14-/12-bit, 250 ksps adcs on board. 2. six true bipolar, high impedance analog inputs. 3. parallel and high speed serial interfaces. 1 protected by u.s. patent no. 6,731,232.
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ad7656 .......................................................................................... 3 ad7657 .......................................................................................... 5 ad7658 .......................................................................................... 7 timing specifications .................................................................. 9 absolute maximum ratings.......................................................... 10 thermal resistance .................................................................... 10 esd caution................................................................................ 10 pin configuration and function descriptions........................... 11 typical performance characteristics ........................................... 14 terminology .................................................................................... 18 theory of operation ...................................................................... 20 converter details ....................................................................... 20 adc transfer function............................................................. 21 reference section ....................................................................... 21 typical connection diagram ................................................... 21 driving the analog inputs ........................................................ 22 interface section......................................................................... 22 application hints ........................................................................... 29 layout .......................................................................................... 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 3 of 32 specifications ad7656-1 v ref = 2.5 v internal/external, av cc = 4.75 v to 5.25 v, dv cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v; for 4 v ref range: v dd = 10 v to 16.5 v, v ss = ?10 v to ?16.5 v; for 2 v ref range: v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v; f sample = 250 ksps, t a = t min to t max , unless otherwise noted. 1 table 1. parameter b version 1 y version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 84 84 db min 85.5 85.5 db typ signal-to-noise ratio (snr) 2 85 85 db min 86.5 86.5 db typ total harmonic distortion (thd) 2 ?90 ?90 db max ?92 ?92 db typ v dd /v ss = 5 v to 10 v ?100 ?100 db typ v dd /v ss = 12 v to 16.5 v peak harmonic or spurious noise (sfdr) 2 ?100 ?100 db typ intermodulation distortion (imd) 2 fa = 50 khz, fb = 49 khz second-order terms ?112 ?112 db typ third-order terms ?107 ?107 db typ aperture delay 10 10 ns max aperture delay matching 4 4 ns max aperture jitter 35 35 ps typ channel-to-channel isolation 2 ?100 ?100 db typ f in on unselected channels up to 100 khz full power bandwidth 12 12 mhz typ @ ?3 db 2 2 mhz typ @ ?0.1 db dc accuracy resolution 16 16 bits no missing codes 15 14 bits min 16 16 bits min @ 25c integral nonlinearity 2 3 4.5 lsb max 1 1 lsb typ positive full-scale error 2 0.75 0.75 % fs max 0.22% fsr typical positive full-scale error matching 2 0.35 0.35 % fs max bipolar zero-scale error 2 0.023 0.023 % fs max 0.004% fsr typical bipolar zero-scale error matching 2 0.038 0.038 % fs max negative full-scale error 2 0.75 0.75 % fs max 0.22% fsr typical negative full-scale error matching 2 0.35 0.35 % fs max analog input see table 8 for min v dd /v ss for each range input voltage ranges 4 v ref 4 v ref v rng bit/range pin = 0 2 v ref 2 v ref v rng bit/range pin = 1 dc leakage current 1 1 a max input capacitance 3 10 10 pf typ 4 v ref range when in track 14 14 pf typ 2 v ref range when in track reference input/output reference input voltage range 2.5 2.5 v min/max dc leakage current 1 1 a max input capacitance 3 18.5 18.5 pf typ ref en/ dis = 1 reference output voltage 2.49/2.51 2.49/2.51 v min/max long-term stability 150 150 ppm typ 1,000 hours reference temperature coefficient 25 25 ppm/c max 6 6 ppm/c typ
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 4 of 32 parameter b version 1 y version 1 unit test conditions/comments logic inputs input high voltage (v inh ) 0.7 v drive 0.7 v drive v min input low voltage (v inl ) 0.3 v drive 0.3 v drive v max input current (i in ) 1 1 a max typically 10 na, v in = 0 v or v drive input capacitance (c in ) 3 10 10 pf max logic outputs output high voltage (v oh ) v drive ? 0.2 v drive ? 0.2 v min i source = 200 a output low voltage (v ol ) 0.2 0.2 v max i sink = 200 a floating-state leakage current 1 1 a max floating-state output capacitance 3 10 10 pf max output coding twos complement conversion rate conversion time 3.1 3.1 s max track-and-hold acquisition time 2, 3 550 550 ns max throughput rate 250 250 ksps parallel interface mode only power requirements v dd 5/15 5/15 v nom min/max for 4 x v ref range, v dd = 10 v to 16.5 v v ss ?5/?15 ?5/?15 v nom min/max for 4 x v ref range, v dd = ?10 v to ?16.5 v av cc 5 5 v nom dv cc 5 5 v nom v drive 3/5 3/5 v nom min/max i total digital i/p s = 0 v or v drive normal mode (static) 28 28 ma max av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, (includes iav cc , iv dd , iv ss , iv drive , idv cc ) v ss = ?16.5 v normal mode (operational) tbd tbd ma max f sample = 250 ksps, av cc = dv cc = v drive = 5.25 v, (includes iav cc , iv dd , iv ss , iv drive , idv cc ) v dd = 16.5 v, v ss = ?16.5 v i ss (operational) 0.25 0.25 ma max v ss = ?16.5 v, f sample = 250 ksps i dd (operational) 0.25 0.25 ma max v dd = 16.5 v, f sample = 250 ksps partial power-down mode 7 7 ma max av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v full power-down mode (stby pin) 80 80 a max sclk on or off, av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v power dissipation av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v normal mode (static) 143 143 mw max normal mode (operational) tbd tbd mw max f sample = 250 ksps partial power-down mode 35 35 mw max full power-down mode (stby pin) 100 100 w max 1 temperature ranges are as follow s: b version is ?40c to +85c, y version is ? 40c to +125c. 2 see the terminology section. 3 sample tested during initial release to ensure compliance.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 5 of 32 ad7657-1 v ref = 2.5 v internal/external, av cc = 4.75 v to 5.25 v, dv cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v; for 4 v ref range: v dd = 10 v to 16.5 v, v ss = ?10 v to ?16.5 v; for 2 v ref range: v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v; f sample = 250 ksps, t a = t min to t max , unless otherwise noted. 1 table 2. parameter b version 1 y version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 81.5 81.5 db min signal-to-noise ratio (snr) 2 82.5 82.5 db min 83.5 83.5 db typ total harmonic distortion (thd) 2 ?90 ?89 db max ?92 ?92 db typ peak harmonic or spurious noise (sfdr) 2 ?100 ?100 db typ intermodulation distortion (imd) 2 fa = 50 khz, fb = 49 khz second-order terms ?109 ?109 db typ third-order terms ?104 ?104 db typ aperture delay 10 10 ns max aperture delay matching 4 4 ns max aperture jitter 35 35 ps typ channel-to-channel isolation 2 ?100 ?100 db typ f in on unselected channels up to 100 khz full power bandwidth 12 12 mhz typ @ ?3 db 2 2 mhz typ @ ?0.1 db dc accuracy resolution 14 14 bits no missing codes 14 14 bits min integral nonlinearity 2 1.5 1.5 lsb max 1 1 lsb typ positive full-scale error 2 0.61 0.61 % fs max 0.183% fsr typical positive full-scale error matching 2 0.3 0.3 % fs max bipolar zero-scale error 2 0.0305 0.0305 % fs max 0.015 % fsr typical bipolar zero-scale error matching 2 0.0427 0.0427 % fs max negative full-scale error 2 0.61 0.61 % fs max 0.183% fsr typical negative full-scale error matching 2 0.3 0.3 % fs max analog input see table 8 for min v dd /v ss for each range input voltage ranges 4 v ref 4 v ref v rng bit/range pin = 0 2 v ref 2 v ref v rng bit/range pin = 1 dc leakage current 1 1 a max input capacitance 3 10 10 pf typ 4 v ref range when in track 14 14 pf typ 2 v ref range when in track reference input/output reference input voltage range 2.5 2.5 v min/max dc leakage current 1 1 a max input capacitance 3 18.5 18.5 pf typ ref en/ dis = 1 reference output voltage 2.49/2.51 2.49/2.51 v min/max long-term stability 150 150 ppm typ 1,000 hours reference temperature coefficient 25 25 ppm/c max 6 6 ppm/c typ logic inputs input high voltage (v inh ) 0.7 v drive 0.7 v drive v min input low voltage (v inl ) 0.3 v drive 0.3 v drive v max input current (i in ) 1 1 a max typically 10 na, v in = 0 v or v drive input capacitance (c in ) 3 10 10 pf max
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 6 of 32 parameter b version 1 y version 1 unit test conditions/comments logic outputs output high voltage (v oh ) v drive ? 0.2 v drive ? 0.2 v min i source = 200 a output low voltage (v ol ) 0.2 0.2 v max i sink = 200 a floating-state leakage current 1 1 a max floating-state output capacitance 3 10 10 pf max output coding twos complement conversion rate conversion time 3.1 3.1 s max track-and-hold acquisition time 2, 3 550 550 ns max throughput rate 250 250 ksps parallel interface mode only power requirements v dd 5/15 5/15 v nom min/max for 4 x v ref range, v dd = 10 v to 16.5 v v ss ?5/?15 ?5/?15 v nom min/max for 4 x v ref range, v dd = ?10 v to ?16.5 v av cc 5 5 v nom dv cc 5 5 v nom v drive 3/5 3/5 v nom min/max i total digital i/p s = 0 v or v drive normal mode (static) 28 28 ma max av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, (includes iav cc , iv dd , iv ss , iv drive , idv cc ) v ss = ?16.5 v normal mode (operational) tbd tbd ma max f sample = 250 ksps, av cc = dv cc = v drive = 5.25 v, (includes iav cc , iv dd , iv ss , iv drive , idv cc ) v dd = 16.5 v, v ss = ?16.5 v i ss (operational) 0.25 0.25 ma max v ss = ?16.5 v, f sample = 250 ksps i dd (operational) 0.25 0.25 ma max v dd = 16.5 v, f sample = 250 ksps partial power-down mode 7 7 ma max av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v full power-down mode (stby pin) 80 80 a max sclk on or off, av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v power dissipation av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v normal mode (static) 143 143 mw max normal mode (operational) tbd tbd mw max f sample = 250 ksps partial power-down mode 35 35 mw max full power-down mode (stby pin) 100 100 w max 1 temperature ranges are as follow s: b version is ?40c to +85c, y version is ? 40c to +125c. 2 see the terminology section. 3 sample tested during initial release to ensure compliance.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 7 of 32 ad7658-1 v ref = 2.5 v internal/external, av cc = 4.75 v to 5.25 v, dv cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v; for 4 v ref range: v dd = 10 v to 16.5 v, v ss = ?10 v to ?16.5 v; for 2 v ref range: v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v; f sample = 250 ksps, t a = t min to t max , unless otherwise noted. 1 table 3. parameter b version 1 y version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 73 73 db min 73.5 73.5 db typ total harmonic distortion (thd) 2 ?88 ?88 db max ?92 ?92 db typ peak harmonic or spurious noise (sfdr) 2 ?97 ?97 db typ intermodulation distortion (imd) 2 fa = 50 khz, fb = 49 khz second-order terms ?106 ?106 db typ third-order terms ?101 ?101 db typ aperture delay 10 10 ns max aperture delay matching 4 4 ns max aperture jitter 35 35 ps typ channel-to-channel isolation 2 ?100 ?100 db typ f in on unselected channels up to 100 khz full power bandwidth 12 12 mhz typ @ ?3 db 2 2 mhz typ @ ?0.1 db dc accuracy resolution 12 12 bits no missing codes 12 12 bits min differential nonlinearity 0.7 0.7 lsb max integral nonlinearity 2 1 1 lsb max positive full-scale error 2 0.6104 0.6104 % fs max 0.244% fsr typical positive full-scale error matching 2 0.366 0.366 % fs max bipolar zero-scale error 2 3 3 lsb max 0.0488% fsr typical bipolar zero-scale error matching 2 3 3 lsb max negative full-scale error 2 0.6104 0.6104 % fs max 0.244% fsr typical negative full-scale error matching 2 0.366 0.366 % fs max analog input see table 8 for min v dd /v ss for each range input voltage ranges 4 v ref 4 v ref v rng bit/range pin = 0 2 v ref 2 v ref v rng bit/range pin = 1 dc leakage current 1 1 a max input capacitance 3 10 10 pf typ 4 v ref range when in track 14 14 pf typ 2 v ref range when in track reference input/output reference input voltage range 2.5 2.5 v min/max dc leakage current 1 1 a max input capacitance 3 18.5 18.5 pf typ ref en/ dis = 1 reference output voltage 2.49/2.51 2.49/2.51 v min/max long-term stability 150 150 ppm typ 1,000 hours reference temperature coefficient 25 25 ppm/c max 6 6 ppm/c typ logic inputs input high voltage (v inh ) 0.7 v drive 0.7 v drive v min input low voltage (v inl ) 0.3 v drive 0.3 v drive v max input current (i in ) 1 1 a max typically 10 na, v in = 0 v or v drive input capacitance (c in ) 3 10 10 pf max
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 8 of 32 parameter b version 1 y version 1 unit test conditions/comments logic outputs output high voltage (v oh ) v drive ? 0.2 v drive ? 0.2 v min i source = 200 a output low voltage (v ol ) 0.2 0.2 v max i sink = 200 a floating-state leakage current 1 1 a max floating-state output capacitance 3 10 10 pf max output coding twos complement conversion rate conversion time 3.1 3.1 s max track-and-hold acquisition time 2, 3 550 550 ns max throughput rate 250 250 ksps parallel interface mode only power requirements v dd 5/15 5/15 v nom min/max for 4 x v ref range, v dd = 10 v to 16.5 v v ss ?5/?15 ?5/?15 v nom min/max for 4 x v ref range, v dd = ?10 v to ?16.5 v av cc 5 5 v nom dv cc 5 5 v nom v drive 3/5 3/5 v nom min/max i total digital i/p s = 0 v or v drive normal mode (static) 28 28 ma max av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, (includes iav cc , iv dd , iv ss , iv drive , idv cc ) v ss = ?16.5 v normal mode (operational) tbd tbd ma max f sample = 250 ksps, av cc = dv cc = v drive = 5.25 v, (includes iav cc , iv dd , iv ss , iv drive , idv cc ) v dd = 16.5 v, v ss = ?16.5 v i ss (operational) 0.25 0.25 ma max v ss = ?16.5 v, f sample = 250 ksps i dd (operational) 0.25 0.25 ma max v dd = 16.5 v, f sample = 250 ksps partial power-down mode 7 7 ma max av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v full power-down mode (stby pin) 80 80 a max sclk on or off, av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v power dissipation av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v normal mode (static) 143 143 mw max normal mode (operational) tbd tbd mw max f sample = 250 ksps partial power-down mode 35 35 mw max full power-down mode (stby pin) 100 100 w max 1 temperature ranges are as foll ows: b version is ?40c to +85 c, y version is ?40c to +125c 2 see the terminology section. 3 sample tested during initial release to ensure compliance.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 9 of 32 timing specifications av cc /dv cc = 4.75 v to 5.25 v, v dd = 5 v to 16.5 v, v ss = ?5 v to ?16.5 v, v drive = 2.7 v to 5.25 v, v ref = 2.5 v internal/external, t a = t min to t max , unless otherwise noted. 1 table 4. limit at t min, t max parameter v drive < 4.75 v v drive = 4.75 v to 5.25 v unit description parallel mode t convert 3 3 s typ conversion time, internal clock t quiet 150 150 ns min minimum quiet time required between bus relinquish and start of next conversion t acq 550 550 ns min acquisition time t 10 25 25 ns min minimum convst low pulse t 1 60 60 ns min convst high to busy high t wake-up 2 2 ms max stby rising edge to convst rising edge 25 25 s max partial power-down mode parallel write operation t 11 15 15 ns min wr pulse width t 12 0 0 ns min cs to wr setup time t 13 5 5 ns min cs to wr hold time t 14 5 5 ns min data setup time before wr rising edge t 15 5 5 ns min data hold after wr rising edge parallel read operation t 2 0 0 ns min busy to rd delay t 3 0 0 ns min cs to rd setup time t 4 0 0 ns min cs to rd hold time t 5 45 36 ns min rd pulse width t 6 45 36 ns max data access time after rd falling edge t 7 10 10 ns min data hold time after rd rising edge t 8 12 12 ns max bus relinquish time after rd rising edge t 9 6 6 ns min minimum time between reads serial interface f sclk 18 18 mhz max frequency of serial read clock t 16 12 12 ns max delay from cs until sdata three-state disabled t 17 2 22 22 ns max data access time after sclk rising edge/cs falling edge t 18 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 19 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 20 10 10 ns min sclk to data valid hold time after sclk falling edge t 21 18 18 ns max cs rising edge to sdata high impedance 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 a buffer is used on the data output pins for this measurement. 200a i ol 200a i oh 1.6v to output pin c l 25pf 05020-002 figure 2. load circuit for digi tal output timing specification
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 10 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to agnd, dgnd ?0.3 v to +16.5 v v ss to agnd, dgnd +0.3 v to ?16.5 v v dd to av cc v cc ? 0.3 v to 16.5 v av cc to agnd, dgnd ?0.3 v to +7 v dv cc to av cc ?0.3 v to av cc + 0.3 v dv cc to dgnd, agnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v v drive to dgnd ?0.3 v to +dv cc + 0.3 v analog input voltage to agnd 1 v ss ? 0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to v drive + 0.3 v digital output voltage to gnd ?0.3 v to v drive + 0.3 v refin to agnd ?0.3 v to av cc + 0.3 v input current to any pin except supplies 2 10 ma operating temperature range b version ?40c to +85c y version ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c pb/sn temperature, soldering reflow (10 sec to 30 sec) 240(+0)c pb-free temperature, soldering reflow 260(+0)c 1 if the analog inputs are being driven from alternative v dd and v ss supply circuitry, a 240 ? series re sistor should be placed on the analog inputs. 2 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. these specifications apply to a four-layer board. table 6. thermal resistance package type ja jc unit 64-lead lqfp 45 11 c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 11 of 32 pin configuration and fu nction descriptions 64 db15 63 wr/ref en/dis 62 h/s sel 61 ser/par/sel 60 av cc 59 agnd 58 refcapc 57 agnd 56 refcapb 55 agnd 54 refcapa 53 agnd 52 agnd 51 refin/refout 50 av cc 49 agnd 47 av cc 46 av cc 45 v5 42 v4 43 agnd 44 agnd 48 v6 41 av cc 40 av cc 39 v3 37 agnd 36 v2 35 av cc 34 av cc 33 v1 38 agnd 2 db13 3 db12 4 db11 7 db8/dout a 6 db9/dout b 5 db10/dout c 1 db14/refbuf en/dis 8 dgnd 9 v drive 10 db7/hben/dcen 12 db5/dcin a 13 db4/dcin b 14 db3/dcin c 15 db2/sel c 16 db1/sel b 11 db6/sclk 17 db0/sel a 18 busy 19 cs 20 rd 21 convst c 22 convst b 23 convst a 24 stby 25 dgnd 26 dv cc 27 range 28 reset 29 w/b 30 v ss 31 v dd 32 agnd pin 1 ad7656-1/ad7657-1/ad7658-1 top view (not to scale) 05020-003 figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic description 54, 56, 58 refcapa, refcapb, refcapc decoupling capacitors are connected to these pins. this decouples the reference buffer for each adc pair. each refcap pin should be decoupled to agnd using a 1 f. 33, 36, 39, 42, 45, 48 v1 to v6 analog input 1 to 6. these are six single-ended an alog inputs. in hardware mode, the analog input range on these channels is determined by the range pi n. in software mode, it is determined by bits rngc to rnga of the control register (see table 10). 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 agnd analog ground. ground reference point for all analog circuitry on the ad7656-1/ad7657-1/ad7658- 1. all analog input signals and any external reference si gnal should be referred to this agnd voltage. all 11 of these agnd pins should be connected to the agnd plane of a system. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 26 dv cc digital power, 4.75 v to 5.25 v. the dv cc and av cc voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. this supply should be decoupled to dgnd, and 10 f and 100 nf decoupling capacitors should be placed on the dv cc pin. 9 v drive logic power supply input. the voltage supplied at this pin determines the operating voltage of the interface. nominally at the same supply as the supply of the host interface. 8, 25 dgnd digital ground. this is the ground reference point for all digital circuitry on the ad7656-1/ad7657- 1/ad7658-1. both dgnd pins should connect to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential an d must not be more than 0.3 v apart, even on a transient basis. 34, 35, 40, 41, 46, 47, 50, 60 av cc analog supply voltage, 4.75 v to 5.25 v. this is the supply voltage for the adc cores. the av cc and dv cc voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 23, 22, 21 convst a, convst b, convst c conversion start input a, b, c. these logic inputs are used to initiate conversions on the adc pairs. convst a is used to initiate simultaneous conversi ons on v1 and v2. convst b is used to initiate simultaneous conversions on v3 and v4. convst c is used to initiate simultaneous conversions on v5 and v6. when convstx switches from low to high, the track-and-hold switch on the selected adc pair switches from track to hold and the conversi on is initiated. these inputs can also be used to place the adc pairs into partial power-down mode.
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 12 of 32 pin no. mnemonic description 19 cs chip select. this active low logic inp ut frames the data transfer. when both cs and rd are logic low in parallel mode, the output bus is enabled and the conversion result is output on the parallel data bus lines. when both cs and wr are logic low in parallel mode, db[15:8] are used to write data to the on-chip control register. in serial mode, the cs is used to frame the seri al read transfer and clock out the msb of the serial output data. 20 rd read data. when both cs and rd are logic low in parallel mode, the output bus is enabled. in serial mode, the rd line should be held low. 63 wr /ref en/ dis write data/reference enable/disable . when h /s sel pin is high and both cs and wr are logic low, db[15:8] are used to write data to the internal control register. when the h /s sel pin is low, this pin is used to enable or disable the internal reference. when h /s sel = 0 and ref en/dis = 0, the internal reference is disabled and an external reference should be applied to the refin/refout pin. when h /s sel = 0 and ref en/dis = 1, the internal reference is enabled and the refin/refout pin should be decoupled. see the reference section. 18 busy busy output. this pin transitions high when a co nversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. a new conversion should not be initiated on the ad 7656-1/ad7657-1/ad7658-1 when the busy signal is high. 51 refin/refout reference input/output. the on-chip reference is available on this pin for use external to the ad7656-1/ad7657-1/ad7658-1. alternatively, the in ternal reference can be disabled and an external reference can be applied to this input. see the reference section. when the internal reference is enabled, this pin should be decoupled using at least a 10 f decoupling cap. 61 ser/par /sel serial/parallel selection input. when this pin is low, the parallel interface is selected. when this pin is high, the serial interface mode is selected. in serial mode, db[10:8] take on their dout[c:a] function, db[0:2] take on their dout select function , db7 takes on its dcen function. in serial mode, db15 and db[13:11] should be tied to dgnd. 17 db0/sel a data bit 0/select dout a. when ser/par = 0, this pin acts as a three- state parallel digital output pin. when ser/par = 1, this pin takes on its sel a function; it is used to configure the serial interface. if this pin is 1, the serial interface operates with one/two/three dout output pins and enables dout a as a serial output. when opera ting in serial mode, this pin should always be = 1. 16 db1/sel b data bit 1/select dout b. when ser/par = 0, this pin acts as a three- state parallel digital output pin. when ser/par = 1, this pin takes on its sel b function; it is used to configure the serial interface. if this pin is 1, the serial interface operates with two/three dout output pins and enables dout b as a serial output. if this pin is 0, the dout b is not enabled to operat e as a serial data output pin and only one dout output pin, dout a, is used. unused serial dout pins should be left unconnected. 15 db2/sel c data bit 2/select dout c. when ser/par = 0, this pin acts as a three- state parallel digital output pin. when ser/par = 1, this pin takes on its sel c function; it is used to configure the serial interface. if this pin is 1, the serial interface operates with three dout output pins and enables dout c as a serial output. if this pin is 0, the dout c is not enabled to oper ate as a serial data output pin. unused serial dout pins should be left unconnected. 14 db3/dcin c data bit 3/daisy-chain input c. when ser/par = 0, this pin acts as a three-state parallel digital output pin. when ser/par = 1 and dcen = 1, this pin acts as daisy-chain input c. when operating in serial mode but not in daisy-chain mo de, this pin should be tied to dgnd. 13 db4/dcin b data bit 4/daisy-chain input b. when ser/par = 0, this pin acts as a three-state parallel digital output pin. when ser/par = 1 and dcen = 1, this pin acts as daisy-chain input b. when operating in serial mode but not in daisy-chain mo de, this pin should be tied to dgnd. 12 db5/dcin a data bit 5/daisy-chain input a. when ser/par is low, this pin acts as a three-state parallel digital output pin. when ser/par = 1 and dcen = 1, this pin acts as daisy-chain input a. when operating in serial mode but not in daisy-chain mo de, this pin should be tied to dgnd. 11 db6/sclk data bit 6/serial clock. when ser/par = 0, this pin acts as a three-state parallel digital output pin. when ser/par = 1, this pin takes on its sclk input function; it is the read serial clock for the serial transfer. 10 db7/hben/dcen data bit 7/high byte enable/daisy-chain enab le. when operating in parallel word mode (ser/par = 0 and w /b = 0), this pin takes on its data bit 7 function. when operating in parallel byte mode (ser/par = 0 and w /b = 1), this pin takes on its hben function. when in this mode and the hben pin is logic high, the da ta is output msb byte first on db [15:8]. when the hben pin is logic low, the data is output lsb byte first on db[15:8]. when ope rating in serial mode (ser/par = 1), this pin takes on its dcen function. when the dc en pin is logic high, the parts operate in daisy- chain mode with db[5:3] taking on their dcin[a:c ] function. when operating in serial mode but not in daisy-chain mode, this pin should be tied to dgnd.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 13 of 32 pin no. mnemonic description 7 db8/dout a data bit 8/serial data output a. when ser/par = 0, this pin acts as a three-state parallel digital output pin. when ser/par = 1 and sel a = 1, this pin takes on its dout a function and outputs serial conversion data. 6 db9/dout b data bit 9/serial data output b. when ser/par = 0, this pin acts as a three-state parallel digital output pin. when ser/par = 1 and sel b = 1, this pin takes on its dout b function and outputs serial conversion data. this configures the se rial interface to have two dout output lines. 5 db10/dout c data bit 10/serial data output c. when ser/par = 0, this pin acts as a three-state parallel digital output pin. when ser/par = 1 and sel c = 1, this pin takes on its dout c function and outputs serial conversion data. this co nfigures the serial interface to have three dout output lines. 4 db11 data bit 11/digital ground. when ser/par = 0, this pin acts as a three-state parallel digital output pin. when ser/par = 1, this pin should be tied to dgnd. 3, 2, 64 db12, db13, db15 data bit 12, 13, 15. when ser/par = 0, these pins act as three-state parallel digital input/output pins. when cs and rd are low, these pins are used to output the conversion result. when cs and wr are low, these pins are used to write to the control register. when ser/par = 1, these pins should be tied to dgnd. for the ad7657, db15 contains a leading zero. for the ad7658, db15, db13, and db12 contain leading zeros. 1 db14/refbuf en /dis data bit 14/refbuf enable /disable. when ser/par =0, this pin acts as a three-state digital input/ output pin. for the ad7657/ad7658, db14 contains a leading zero. when ser/par = 1, this pin can be used to enable or disable the internal reference buffers. 28 reset reset input. when set to logic high, this pi n resets the ad7656-1/ad7657-1/ad7658-1. the current conversion, if any, is aborted. the internal register is set to all 0s. in hardware mode, the ad7656- 1/ad7657-1/ad7658-1 are configured depending on the lo gic levels on the hardware select pins. in all modes, the parts should receive a reset pulse after power-up. the reset high pulse should be typically 100 ns wide. after the reset pulse, th e ad7656-1/ad7657-1/ad7658-1 needs to see a valid convst pulse in order to initiate a conversion; this should consist of a high-to-low convst edge followed by a low-to-high convst edge. the convst signal should be high during the reset pulse. 27 range analog input range selection. logic input. the logi c level on this pin determines the input range of the analog input channels. when th is pin is logic 1 at the falling edge of busy, the range for the next conversion is 2 v ref . when this pin is logic 0 at the falling edge of busy, the range for the next conversion is 4 v ref . in hardware select mode, the range pin is checked on the falling edge of busy. in software mode (h /s sel = 1), the range pin can be tied to dgnd and the input range is determined by the rnga, rngb, and rngc bits in the control register. 31 v dd positive power supply voltage. this is the posi tive supply voltage for the analog input section. 30 v ss negative power supply voltage. this is the negative supply voltage for the analog input section. 24 stby standby mode input. this pin is used to put all six on-chip adcs into standby mode. the stby pin is high for normal operation and low for standby operation. 62 h /s sel hardware /software select input. logic input. when h /s sel = 0, the ad7656-1/ad7657-1/ad7658-1 operate in hardware select mode, and the adc pairs to be simultaneously sampled are selected by the convst pins. when h /s sel = 1, the adc pairs to be sampled simultaneously are selected by writing to the control register. in serial mode, convst a is used to initiate conversions on the selected adc pairs. 29 w /b word /byte input. when this pin is logic low, da ta can be transferred to and from the ad7656- 1/ad7657-1/ ad7658-1 using the parallel data lines db[15: 0]. when this pin is logic high, byte mode is enabled. in this mode, data is transferred using data lines db[15:8] and db[7] takes on its hben function. to obtain the 16-bit conversion result, 2-byte reads are required. in serial mode, this pin should be tied to dgnd.
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 14 of 32 typical performance characteristics 0 ?160 0 frequency (khz) (db) 125 05020-030 ?20 ?40 ?60 ?80 ?100 ?120 ?140 25 50 75 100 v dd /v ss = 15v av cc /dv cc /v drive = +5v internal reference 10v range t a = 25c f s = 250ksps f in = 50khz snr = +87.33db sinad = +87.251db thd = ?104.32db sfdr = ?104.13db figure 4. ad7656-1 fft for 10 v range 0 ?160 0 frequency (khz) (db) 125 05020-031 ?20 ?40 ?60 ?80 ?100 ?120 ?140 25 50 75 100 v dd /v ss = 12v av cc /dv cc /v drive = +5v internal reference 5v range t a = 25c f s = 250ksps f in = 50khz snr = +86.252db sinad = +86.196db thd = ?105.11db sfdr = ?98.189db figure 5. ad7656-1 fft for 5 v range 2.0 ?2.0 0 10k 20k 30k 40k 50k 60k 65535 05020-017 code inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps 2 v ref range inl wcp = 0.64lsb inl wcn = ?0.76lsb figure 6. ad7656-1 typical inl 2.0 ?2.0 0 10k 20k 30k 40k 50k 60k 65535 05020-016 code dnl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps 2 v ref range dnl wcp = 0.81lsb dnl wcn = ?0.57lsb figure 7. ad7656-1 typical dnl 0 2000 4000 6000 8000 10000 12000 14000 16383 05020-035 inl (lsb) code 2.0 ?2.0 1.6 0.8 0 ?0.8 ?1.6 1.2 0.4 ?0.4 ?1.2 av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps 2 v ref range figure 8. ad7657-1 typical inl 2.0 ?2.0 1.6 0.8 0 ?0.8 ?1.6 1.2 0.4 ?0.4 ?1.2 0 2000 4000 6000 8000 10000 12000 14000 16383 dnl (lsb) code 05020-034 av cc /dv cc /v drive = +5v v dd /v ss = 12v figure 9. ad7657-1 typical dnl
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 15 of 32 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4095 05020-033 inl (lsb) code av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps 2 v ref range figure 10. ad7658 typical inl 05020-032 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4095 dnl (lsb) code av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps 2 v ref range figure 11. ad7658 typical dnl 90 60 10 1000 05020-023 analog input frequency (khz) sinad (db) 100 85 80 75 70 65 av cc /dv cc /v drive = +5.25v v dd /v ss = 16.5v 10v range av cc /dv cc / v drive = +5v v dd /v ss = 12v 5v range av cc /dv cc / v drive = +5v v dd /v ss = 5.25v 5v range av cc /dv cc / v drive = +4.75 v v dd /v ss = 10v 10v range f sample = 250ksps internal reference t a = 25c figure 12. ad7656-1 sinad vs. input frequency ? 60 ?120 10 1000 05020-022 analog input frequency (khz) thd (db) 100 ?70 ?80 ?90 ?100 ?110 av cc /dv cc / v drive = +5v v dd /v ss = 12v 5v range av cc /dv cc / v drive = +5.25v v dd /v ss = 16.5v 10v range f sample = 250ksps internal reference t a = 25c av cc /dv cc /v drive = +5v v dd /v ss = 5.25v 5v range av cc /dv cc / v drive = +4.75v v dd /v ss = 10v 10v range figure 13. ad7656 thd vs. input frequency ? 60 ?120 10 100 05020-026 analog input frequency (khz) thd (db) ?70 ?80 ?90 ?100 ?110 v dd /v ss = 16.5v av cc /dv cc /v drive = +5.25v t a = 25c internal reference 4 v ref range r source = 1000 ? r source = 10 ? r source = 100 ? r source = 50 ? r source = 220 ? figure 14. ad7656 thd vs. input frequency for various source impedances, 4 x v ref range ? 40 ?120 10 100 05020-027 analog input frequency (khz) thd (db) ?50 ?60 ?70 ?80 ?90 ?100 ?110 v dd /v ss = 12v av cc /dv cc /v drive = +5v t a = 25c internal reference 2 v ref range r source = 1000 ? r source = 100 ? r source = 50 ? r source = 220 ? r source = 10 ? figure 15. ad7656-1 thd vs. input frequency for various source impedances, 2 x v ref range
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 16 of 32 ?55 125 05020-018 temperature (c) reference voltage (v) ?35 ?15 5 25 45 65 85 105 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 av cc /dv cc /v drive = +5v v dd /v ss = 12v figure 16. reference voltage vs. temperature 3.20 2.70 ?55 125 05020-019 temperature (c) conversion time (s) 3.15 3.10 3.05 3.00 2.95 2.90 2.85 2.80 2.75 ?35 ?15 5 25 45 65 85 105 av cc /dv cc /v drive = +5v v dd /v ss = 12v figure 17. conversion time vs. temperature 3500 0 ?5 code number of occurrences 3 3000 2500 2000 1500 1000 500 ?4 ?3 ?2 ?1 0 1 2 v dd /v ss = 15v av cc /dv cc /v drive = +5v internal reference 8192 samples 05020-029 25 168 1532 3212 2806 392 57 0 0 figure 18. ad7656 histogram of codes 100 40 30 530 05020-021 supply ripple frequency (khz) psrr (db) 90 80 70 60 50 80 130 180 230 280 330 380 430 480 v dd v ss f sample = 250ksps 2 v ref range internal reference t a = 25c f in = 10khz 100nf on v dd and v ss figure 19. psrr vs. supply ripple frequency ?40 140 05020-025 temperature (c) snr (db) ?200 20406080100120 83.0 83.5 84.0 84.5 85.0 85.5 86.0 86.5 87.0 5v range, av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps f in = 50khz internal reference 10v range, av cc /dv cc /v drive = +5.25v v dd /v ss = 16.5v figure 20.ad7656 snr vs. temperature ? 100 ?107 ?40 140 05020-024 temperature (c) thd (db) ?101 ?102 ?103 ?104 ?105 ?106 ?200 20406080100120 10v range, av cc /dv cc /v drive = +5.25v v dd /v ss = 16.5v 5v range, av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps f in = 50khz internal reference figure 21. ad7656-1 thd vs. temperature
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 17 of 32 120 60 0 05020-028 frequency of input noise (khz) channel-to-channel isolation (db) av cc /dv cc /v drive = 5v v dd /v ss = 12v t a = 25c internal reference 2 v ref range 30khz on selected channel 110 100 90 80 70 20 40 60 80 100 120 140 figure 22. channel-to-channel isolation 30 0 ?40 100 05020-020 temperature (c) dynamic current (ma) 25 20 15 10 5 ?200 20406080 10v range 5v range av cc /dv cc /v drive = +5v f sample = 250ksps for 5v range v dd /v ss = 12v for 10v range v dd /v ss = 16.5v figure 23. dynamic current vs. temperature
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 18 of 32 terminology integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a ? lsb below the first code transition and full scale at ? lsb above the last code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, that is, agnd ? 1 lsb. bipolar zero code error match the difference in bipolar zero code error between any two input channels. positive full-scale error the deviation of the last code transition (011110) to (011111) from the ideal (+4 v ref ? 1 lsb, +2 v ref ? 1 lsb) after adjusting for the bipolar zero code error. positive full-scale error match the difference in positive full-scale error between any two input channels. negative full-scale error the deviation of the first code transition (10000) to (10001) from the ideal (?4 v ref + 1 lsb, ?2 v ref + 1 lsb) after adjusting for the bipolar zero code error. negative full-scale error match the difference in negative full-scale error between any two input channels. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of the conversion. the track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1 lsb, after the end of the conversion. see the track-and-hold section for more details. signal-to-(noise + distortion) ratio the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2, excluding dc). the ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to- ( noise + distortio n) = (6.02 n + 1.76) db thus, this is 98 db for a 16-bit converter, 86.04 db for a 14-bit converter, and 74 db for a 12-bit converter. total harmonic distortion (thd) the ratio of the rms sum of the harmonics to the fundamental. for the ad7656-1/ad7657-1/ad7658-1, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 ) db ( v v v v v v thd + + + + = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second- order terms include (fa + fb) and (fa ? fb), and the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7656-1/ad7657-1/ad7658-1 are tested using the ccif standard in which two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 19 of 32 power supply rejection (psr) variations in power supply affect the full-scale transition but not the converters linearity. power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. see the typical performance characteristics section. figure 19 shows the power supply rejection ratio vs. supply ripple frequency for the ad7656-1/ad7657-1/ad7658-1. the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 200 mv p-p sine wave applied to the adcs v dd and v ss supplies of frequency f s psrr (db) = 10 log ( pf / pf s ) where: pf is equal to the power at frequency f in the adc output. pf s is equal to the power at frequency f s coupled onto the v dd and v ss supplies. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full-scale, 100 khz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 30 khz signal.
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc | page 20 of 32 theory of operation converter details the ad7656-1/ad7657-1/ad7658-1 are high speed, low power converters that allow the simultaneous sampling of six on-chip adcs. the analog inputs on the ad7656-1/ad7657- 1/ad7658-1 can accept true bipolar input signals. the range pin/rng bits are used to select either 4 v ref or 2 v ref as the input range for the next conversion. each ad7656-1/ad7657-1/ad7658-1 contains six sar adcs, six track-and-hold amplifiers, an on-chip 2.5 v reference, reference buffers, and high speed parallel and serial interfaces. the parts allow the simultaneous sampling of all six adcs when all three convst signals are tied together. alternatively, the six adcs can be grouped into three pairs. each pair has an associated convst signal used to initiate simultaneous sampling on each adc pair, on four adcs, or on all six adcs. convst a is used to initiate simultaneous sampling on v1 and v2, convst b is used to initiate simultaneous sampling on v3 and v4, and convst c is used to initiate simultaneous sampling on v5 and v6. a conversion is initiated on the ad7656-1/ad7657-1/ad7658- 1 by pulsing the convstx input. on the rising edge of convstx, the track-and-hold of the selected adc pair is placed into hold mode and the conversions are started. after the rising edge of convstx, the busy signal goes high to indicate that the conversion is taking place. the conversion clock for the ad7656-1/ad7657-1/ad7658-1 is internally generated, and the conversion time for the parts is 3 s. the busy signal returns low to indicate the end of conversion. on the falling edge of busy, the track-and-hold returns to track mode. data can be read from the output register via the parallel or serial interface. track-and-hold section the track-and-hold amplifiers on the ad7656-1/ad7657- 1/ad7658-1 allow the adcs to accurately convert an input sine wave of full-scale amplitude to 16-/14-/12-bit resolution respectively. the input bandwidth of the track-and-hold amplifiers is greater than the nyquist rate of the adc, even when the ad7656-1/ ad7657-1/ad7658-1 are operating at its maximum throughput rate. the parts can handle input frequencies of up to 12 mhz. the track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of convstx. the aperture time for the track-and-hold (that is, the delay time between the external convstx signal actually going into hold) is 10 ns. this is well matched across all six track-and-holds on one device and from device to device. this allows more than six adcs to be sampled simultaneously. the end of the conversion is signaled by the falling edge of busy, and it is at this point that the track-and-holds return to track mode and the acquisition time begins. analog input section the ad7656-1/ad7657-1/ad7658-1 can handle true bipolar input voltages. the logic level on the range pin or the value written to the rngx bits in the control register determines the analog input range on the ad7656-1/ad7657-1/ad7658-1 for the next conversion. when the range pin/rngx bit is 1, the analog input range for the next conversion is 2 v ref . when the range pin/rngx bit is 0, the analog input range for the next conversion is 4 v ref . d1 d2 v dd c2 r1 v 1 v ss c1 05020-004 figure 24. equivalent analog input structure figure 24 shows an equivalent circuit of the analog input structure of the ad7656-1/ad7657-1/ad7658-1. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the v dd and v ss supply rails by more than 300 mv. signals exceeding this value cause these diodes to become forward-biased and to start conducting current into the substrate. the maximum current these diodes can conduct without causing irreversible damage to the parts is 10 ma. capacitor c1 in figure 24 is typically about 4 pf and can be attributed primarily to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a switch (track-and- hold switch). this resistor is typically about 25 ?. capacitor c2 is the adc sampling capacitor and has a capacitance of 10 pf typically. the ad7656-1/ad7657-1/ad7658-1 require v dd and v ss dual supplies for the high voltage analog input structures. these supplies must be equal to or greater than the analog input range (see table 8 for the requirements on these supplies for each analog input range). the ad7656-1/ad7657-1/ad7658-1 require a low voltage av cc supply of 4.75 v to 5.25 v to power the adc core, a dv cc supply of 4.75 v to 5.25 v for the digital power, and a v drive supply of 2.7 v to 5.25 v for the interface power. to meet the specified performance when using the minimum supply voltage for the selected analog input range, it can be necessary to reduce the throughput rate from the maximum throughput rate. table 8. minimum v dd /v ss supply voltage requirements analog input range (v) reference voltage (v) full scale input (v) minimum v dd /v ss (v) 4 v ref +2.5 10 10 4 v ref +3.0 12 12
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 21 of 32 2 v ref +2.5 5 5 2 v ref +3.0 6 6 adc transfer function the output coding of the ad7656-1/ad7657-1/ad7658-1 is twos complement. the designed code transitions occur midway between successive integer lsb values, that is, 1/2 lsb, 3/2 lsb. the lsb size is fsr/65,536 for the ad7656-1, fsr/16384 for the ad7657-1, and fsr/4096 for the ad7658-1. the ideal transfer characteristic is shown in figure 25. 011...111 011...110 000...001 000...000 111...111 ?fsr/2 + 1/2lsb +fsr/2 ? 3/2lsb agnd ? 1lsb analog input adc code 100...010 100...001 100...000 05020-005 figure 25. ad7656-1/ad7657-1/ad7658-1 transfer characteristic the lsb size is dependent on the analog input range selected (see table 9). reference section the rfin/refout pin either allows access to the ad7656-1/ ad7657-1/ad7658-1s 2.5 v reference or it allows an external reference to be connected, providing the reference source for each parts conversions. the ad7656-1/ad7657-1/ad7658-1 can accommodate a 2.5 v to 3 v external reference range. when using an external reference, the internal reference needs to be disabled. after a reset, the ad7656-1/ad7657-1/ad7658- 1 default to operating in external reference mode with the internal reference buffers enabled. the internal reference can be enabled in either hardware or software mode. to enable the internal reference in hardware mode, the h /s sel pin = 0 and the ref en/ dis pin = 1. to enable the internal reference in software mode, h /s sel = 1 and a write to the control register is necessary to make db9 of the register = 1. for the internal reference mode, the refin/refout pin should be decoupled using a 1 f capacitor. the ad7656-1/ad7657-1/ad7658-1 contain three on-chip reference buffers. each of the three adc pairs has an associated reference buffer. these reference buffers require external decoupling capacitors on refcapa, refcapb, and refcapc pins, and 1 f decoupling capacitors should be placed on these refcap pins. the internal reference buffers can be disabled in software mode by writing to bit db8 in the internal control register. if operating the devices in serial mode, the internal reference buffers can be disabled in hardware mode by setting the db14/refbuf / en dis pin high. if the internal reference and its buffers are disabled, an external buffered reference should be applied to the refcap pins. typical connection diagram figure 26 shows the typical connection diagram for the ad7656-1/ad7657-1/ad7658-1. there are eight av cc supply pins on the parts. the av cc supply is the supply that is used for the ad7656-1/ad7657-1/ad7658-1 conversion process, therefore, it should be well decoupled. the avcc supply pins should be decoupled using a 1 f capacitor. the ad7656- 1/ad7657-1/ ad7658-1 can operate with the internal reference or an externally applied reference. in this configuration, the parts are configured to operate with the external reference. the refin/refout pin is decoupled with a 1 f cap . the three internal reference buffers are enabled. each of the refcap pins are decoupled with a 1 f capacitor. if the same supply is being used for the av cc supply and dv cc supply, a ferrite or small rc filter should be placed between the supply pins. agnd pins are connected to the agnd plane of the system. the dgnd pins are connected to the digital ground plane in the system. the agnd and dgnd planes should be connected together at one place in the system. this connection should be made as close as possible to the ad7656-1/ad7657-1/ad7658- 1 in the system. table 9. lsb size for each analog input range range ad7656-1 ad7657-1 ad7658-1 input range 10 v 5 v 10 v 5 v 10 v 5 v lsb size 0.305 mv 0.152 mv 1.22 mv 0.610 mv 4.88 mv 2.44mv fs range 20 v/65,536 10 v/65,536 20 v/16384 10 v/16384 20 v/4096 10 v/4096
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 22 of 32 + + + dv cc + dv cc av cc agnd dgnd v drive dgnd v dd agnd + v ss agnd + + refcapa, b, c agnd refin/out agnd d0 to d15 convst a, b, c cs rd busy ser/par h/s w/b range reset stby v drive ad7656-1/ ad7657-1/ ad7658-1 1f p/c/dsp 1f 1f 1f 1f 1f 1f digital supply voltage +3v or +5v analog supply voltage 5v 1 +9.5v to +16.5v supply 2.5v ref six analog inputs ?9.5v to ?16.5v supply parallel interface figure 26. typical connection diagram the v drive supply is connected to the same supply as the processor. the voltage on v drive controls the voltage value of the output logic signals. the v dd and v ss signals should be decoupled with a minimum 1 f decoupling capacitor. these supplies are used for the high voltage analog input structures on the ad7656-1/ad7657- 1/ad7658-1 analog inputs. driving the analog inputs together, the driver amplifier and the analog input circuit used for the ad7656-1 must settle for a full-scale step input to a 16- bit level (0.0015%), which is within the specified 550 ns acquisition time of the ad7656-1. the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7656-1. the driver also needs to have a thd performance suitable to that of the ad7656-1. the ad8021 meets all these requirements. the ad8021 needs an external compensation capacitor of 10 pf. if a dual version of the ad8021 is required, the ad8022 can be used. the ad8610 and the ad797 can also be used to drive the ad7656-1/ad7657-1/ad7658-1. interface section the ad7656-1/ad7657-1/ad7658-1 provide two interface options, a parallel interface and a high speed serial interface. the required interface mode is selected via the ser/ par pin. the parallel interface can operate in word ( w /b = 0) or byte ( w /b = 1) mode. the interface modes are discussed in the following sections. parallel interface (ser/ par = 0) the ad7656-1/ad7657-1/ad7658-1 consist of six 16-/14-/12- bit adcs respectively. a simultaneous sample of all six adcs can be performed by connecting all three convst pins together, convst a, convst b, and convst c. the ad7656-1/ad7657-1/ ad 7658-1 need to see a convst pulse in order to initiate a conversion; this should consist of a falling convst edge followed by a rising convst edge. the rising edge of convstx initiates simultaneous conversions on the selected adcs. the ad7656-1/ad7657-1/ad7658-1 contain an on-chip oscillator that is used to perform the conversions. the conversion time, t conv , is 3 s. the busy signal goes low to indicate the end of conversion. the falling edge of the busy signal is used to place the track-and-hold into track mode. the ad7656-1/ad7657-1/ad7658-1 also allow the six adcs to be converted simultaneously in pairs by pulsing the three convst pins independently. convst a is used to initiate simultaneous conversions on v1 and v2, convst b is used to initiate simultaneous conversions on v3 and v4, and convst c is used to initiate simultaneous conversions on v5 and v6. the conversion results from the simultaneously sampled adcs are stored in the output data registers. data can be read from th e ad7656-1/ad7657-1/ad7658-1 via the parallel data bus with standard cs and rd signals ( w /b = 0). to read the data over the parallel bus, ser/ par should be tied low. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines db0 to db15 leave their high impedance state when both cs and rd are logic low.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 23 of 32 the cs signal can be permanently tied low, and the rd signal can be used to access the conversion results. a read operation can take place after the busy signal goes low. the number of required read operations depends on the number of adcs that are simultaneously sampled (see figure 27). if convst a and convst b are simultaneously brought low, four read operations are required to obtain the conversion results from v1, v2, v3, and v4. if convst a and convst c are simultaneously brought low, four read operations are required to obtain the conversion results from v1, v2, v5, and v6. the conversion results are output in ascending order. for the ad7657, db15 and db14 contain two leading zeros and db[13:0] output the 14-bit conversion result. for the ad7658, db[15:12] contain four leading zeros and db[11:0] output the 12-bit conversion result. when using the three convst signals to independently initiate conversions on the three adc pairs, care should be taken to ensure that a conversion is not initiated on a channel pair when the busy signal is high. it is also recommended not to initiate a conversion during a read sequence because doing so can affect the performance of the conversion. for the specified performance, it is recommended to perform the read after the conversion. for unused input channel pairs, the associated convstx pin should be tied to v drive . if there is only an 8-bit bus available, the ad7656-1/ad7657-1/ ad7658-1 interface can be configured to operate in byte mode ( w /b = 1). in this configuration, the db7/hben/dcen pin takes on its hben function. each channel conversion result from the ad7656-1/ad7657-1/ad7658-1 can be accessed in two read operations, with 8-bits of data provided on db15 to db8 for each of the read operations (see figure 28). the hben pin determines whether the read operation first accesses the high byte or the low byte of the 16-bit conversion result. to always access the low byte first on db15 to db8, the hben pin should be tied low. to always access the high byte first on db15 to db8, the hben pin should be tied high. in byte mode when all three convst pins are pulsed together to initiate simultaneous conversions on all six adcs, 12 read operations are necessary to read back th e six 16-/14-/12-bit conversion results. db[6:0] should be left unconnected in byte mode. v1 v2 v3 v4 v5 v6 convst a, convst b, convst c busy cs rd data t quiet t 7 t 8 t 9 t 4 t 2 t 3 t 5 t 6 t acq t conv 0 5020-007 t 10 figure 27. parallel interface timing diagram ( w /b = 0) low byte high byte db15 to db8 cs rd t 3 t 6 t 7 t 8 t 4 t 5 t 9 05020-008 figure 28. parallel interfaceread cycle for byte mode of operation. ( w /b = 1, hben = 0)
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 24 of 32 software selection of adcs the h /s sel pin determines the source of the combination of adcs that are to be simultaneously sampled. when the h /s sel pin is logic low, the combination of channels to be simultaneously sampled is determined by the convst a, convst b, and convst c pins. when the h /s sel pin is logic high, the combination of channels selected for simultaneous sampling is determined by the contents of the control register db15 to control register db13. in this mode, a write to the control register is necessary. the control register is an 8-bit write only register. data is written to this register using the cs and wr pins and the db[15:8] data pins (see figure 29). the control register is shown in table 10. to select an adc pair to be simultaneously sampled, set the corresponding data line high during the write operation. the ad7656-1/ad7657-1/ad7658-1 control register allows individual ranges to be programmed on each adc pair. db12 to db10 in the control register are used to program the range on each adc pair. after a reset occurs on the ad7656-1/ad7657-1/ad7658-1, the control register contains all zeros. the convst a signal is used to initiate a simultaneous conversion on the combination of channels selected via the control register. the convst b and convst c signals can be tied low when operating in software mode ( h /s sel = 1). the number of read pulses required depends on the number of adcs selected in the control register and on whether the devices are operating in word or byte mode. the conversion results are output in ascending order. during the write operation, data bus bit db15 to bit db8 are bidirectional and become inputs to the control register when rd is logic high and cs and wr are logic low. the logic state on db15 through db8 is latched into the control register when wr goes logic high. table 10. control register bit function descriptions (default all 0s) db15 db14 db13 db12 db11 db10 db9 db8 vc vb va rngc rngb rnga refen refbuf table 11. bit mnemonic comment db15 vc this bit is used to select analog inputs v5 and v6 for the next conversion. when this bit = 1, v5 and v6 are simultaneously converted on the next convst a rising edge. db14 vb this bit is used to select analog inputs v3 and v4 for the next conversion. when this bit = 1, v3 and v4 are simultaneously converted on the next convst a rising edge. db13 va this bit is used to select analog inputs v1 and v2 for the next conversion. when this bit = 1, v1 and v2 are simultaneously converted on the next convst a rising edge. db12 rngc this bit is used to select the analog input range for analog inputs v5 and v6. when this bit = 1, the 2 v ref mode is selected for the next conversion. when this bit = 0, the 4 v ref mode is selected for the next conversion. db11 rngb this bit is used to select the analog input range for analog inputs v3 and v4. when this bit = 1, the 2 v ref mode is selected for the next conversion. when this bit = 0, the 4 v ref mode is selected for the next conversion. db10 rnga this bit is used to select the analog input range for analog inputs v1 and v2. when this bit = 1, the 2 v ref mode is selected for the next conversion. when this bit = 0, the 4 v ref mode is selected for the next conversion. db9 refen this bit is used to select the internal reference or an external reference. when this bit = 0, the external reference mode is selected. when this bit = 1, the internal reference is selected. db8 refbuf this bit is used to select between using the internal reference buffers and choosing to bypass these reference buffers. when this bit = 0, the internal reference buffers are enabled and decoupling is required on the refcap pins. when this bit = 1, the internal reference buffers are disabled and a buffered reference should be applied to the refcap pins. data db15 to db8 cs t 13 t 15 t 14 t 11 t 12 wr 05020-009 figure 29. parallel interfacewrite cycle for word mode ( w /b= 0)
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc | page 25 of 32 changing the analog input range ( h /s sel = 0) the ad7656-1/ad7657-1/ad7658-1 range pin allows the user to select either 2 v ref or 4 v ref as the analog input range for the six analog inputs. when the h /s sel pin is low, the logic state of the range pin is sampled on the falling edge of the busy signal to determine the range for the next simultaneous conversion. when the range pin is logic high at the falling edge of the busy signal, the range for the next conversion is 2 v ref . when the range pin is logic low at the falling edge of the busy signal, the range for the next conversion is 4 v ref . after a reset pulse, the range is updated on the first falling busy edge after the reset pulse. changing the analog input range ( h /s sel = 1) when the h /s sel pin is high, the range can be changed by writing to the control register. db[12:10] in the control register are used to select the analog input ranges for the next conversion. each analog input pair has an associated range bit, allowing independent ranges to be programmed on each adc pair. when the rngx bit = 1, the range for the next conversion is 2 v ref . when the rngx bit = 0, the range for the next conversion is 4 v ref . serial interface (ser/ par = 1) by pulsing one, two, or all three convstx signals, the ad7656-1/ad7657-1/ad7658-1 use their on-chip trimmed oscillator to simultaneously convert the selected channel pairs on the rising edge of convstx. after the rising edge of convstx, the busy signal goes high to indicate that the conversion has started. it returns low when the conversion is complete 3 s later. the output register is loaded with the new conversion results, and data can be read from the ad7656- 1/ad7657-1/ad7658-1. to read the data back from the parts over the serial interface, ser/ par should be tied high. the cs and sclk signals are used to transfer data from the ad7656- 1/ad7657-1/ad7658-1. the parts have three dout pins, dout a, dout b, and dout c. data can be read back from the each part using one, two, or all three dout lines. figure 30 shows six simultaneous conversions and the read sequence using three dout lines. also in figure 30, 32 sclk transfers are used to access data from the ad7656-1/ad7657-1/ ad7658-1; however, two 16 sclk individually framed transfers with the cs signal can also be used to access the data on the three dout lines. when operating the ad7656-1/ad7657- 1/ad7658-1 in serial mode with conversion data clocking out on all three dout lines, db0/sel a, db1/sel b, and db2/sel c should be tied to v drive . these pins are used to enable the dout a to dout c lines, respectively. if it is required to clock conversion data out on two data out lines, dout a and dout b should be used. to enable dout a and dout b, db0/sel a and db1/sel b should be tied to v drive and db2/sel c should be tied low. when six simultaneous conversions are performed and only two dout lines are used, a 48 sclk transfer can be used to access the data from the ad7656-1/ad7657-1/ad7658-1. the read sequence is shown in figure 31 for a simultaneous conversion on all six adcs using two dout lines. if a simultaneous conversion occurred on all six adcs, and only two dout lines are used to read the results from the ad7656-1/ ad7657-1/ad7658-1. dout a clocks out the result from v1, v2, and v5, while dout b clocks out the results from v3, v4, and v6. data can also be clocked out using just one dout line, in which case dout a should be us ed to access the conversion data. to configure the ad7656-1/ad7657-1/ad7658-1 to operate in this mode, db0/sel a should be tied to v drive and db1/sel b and db2/sel c should be tied low. the disadvantage of using just one dout line is that the throughput rate is reduced. data can be accessed from the ad7656-1/ad7657-1/ad7658-1 using one 96 sclk transfer, three 32 sclk individually framed transfers, or six 16 sclk individually framed transfers. in serial mode, the rd signal should be tied low. the unused dout line(s) should be left unconnected in serial mode. serial read operation figure 32 shows the timing diagram for reading data from the ad7656-1/ad7657-1/ad7658-1 in serial mode. the sclk input signal provides the clock source for the serial interface. the cs signal goes low to access data from the ad7656-1/ad7657- 1/ad7658-1. the falling edge of cs takes the bus out of three- state and clocks out the msb of the 16-bit conversion result. the adcs output 16 bits for each conversion result; the data stream of the ad7656-1 consists of 16 bits of conversion data provided msb first. the data stream for the ad7657-1 consists of two leading zeros followed by 14 bits of conversion data msb first. the data stream for the ad7658-1 consists of four leading zeros and 12 bits of conversion data provided msb first. the first bit of the conversion result is valid on the first sclk falling edge after the cs falling edge. the subsequent 15 data bits are clocked out on the rising edge of the sclk signal. data is valid on the sclk falling edge. to access each conversion result, 16 clock pulses must be provided to the ad7656- 1/ad7657-1/ ad7658-1. figure 32 shows how a 16 sclk read is used to access the conversion results.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 26 of 32 v1 v2 convst a, convst b, convst c busy cs dout a dout b dout c 32 v3 v4 v5 v6 sclk 16 t quiet t acq t conv 05020-010 figure 30. serial interface with three dout lines v1 v2 v5 dout a dout b 48 v3 v4 v6 sclk cs 05020-011 figure 31. serial interface with two dout lines busy acquisition conversion acquisition sclk cs dout a, b, c db15 db14 db13 db1 db0 t acq t 10 t conv t 2 t 1 t quiet t 21 t 20 t 17 t 16 t 18 t 19 05020-012 convst a, convst b, convst c figure 32. serial read operation
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc | page 27 of 32 daisy-chain mode (dcen = 1, ser/ par = 1) when reading conversion data back from the ad7656- 1/ad7657-1/ ad7658-1 using their three/two/one dout pins, it is possible to configure the parts to operate in daisy-chain mode, using the dcen pin. this daisy-chain feature allows multiple ad7656-1/ ad7657-1/ad 7658-1 devices to be cascaded together and is useful for reducing component count and wiring connections. an example connection of two devices is shown in figure 33. this configuration shows two dout lines being used. simultaneous sampling of the 12 analog inputs is possible by using a common convstx signal. the db5, db4, and db3 data pins are used as data input pins dcin [a:c] for the daisy- chain mode. the rising edge of convst is used to initiate a conversion on the ad7656-1/ad7657-1/ad7658-1. after the busy signal has gone low to indicate that the conversion is complete, the user can begin to read the data from the two devices. figure 34 shows the serial timing diagram when operating two ad7656- 1/ad7657-1/ ad7658-1 devices in daisy-chain mode. the cs falling edge is used to frame the serial transfer from the ad7656-1/ad7657-1/ad7658-1 devices, to take the bus out of three-state, and to clock out the msb of the first conversion result. in the example shown in figure 34, all 12 adc channels are simultaneously sampled. two dout lines are used to read the conversion results in this example. cs frames a 96 sclk transfer. during the first 48 sclks, the conversion data is transferred from device 2 to device 1. dout a on device 2 transfers conversion data from v1, v2, and v5 into dcin a in device 1. dout b on device 2 transfers conversion results from v3, v4, and v6 to dcin b in device 1. during the first 48 sclks, device 1 transfers data into the digital host. dout a on device 1 transfers conversion data from v1, v2, and v5. dout b on device 1 transfers conversion data from v3, v4, and v6. during the last 48 sclks, device 2 clocks out zeros and device 1 shifts the data clocked in from device 2 during the first 48 sclks into the digital host. this example can also be implemented using six 16 sclk individually framed transfers if dcen remains high during the transfers. figure 35 shows the timing if two ad7656-1/ad7657- 1/ad7658-1 devices are configured in daisy-chain mode and are operating with three dout lines. assuming a simultaneous sampling of all 12 inputs occurs, the cs frames a 64 sclk transfer during the read operation. during the first 32 sclks of this transfer, the conversion results from device 1 are clocked into the digital host and the conversion results from device 2 are clocked into device 1. during the last 32 sclks of the transfer, the conversion results from device 2 are clocked out of device 1 and into the digital host. device 2 clocks out zeros. standby/partial power-down modes of operation each adc pair can be individually placed into partial power- down mode by bringing the convstx signal low before the falling edge of busy. to power the adc pair back up, the convstx signal should be brought high to tell the adc pair to power up and place the track-and-hold into track mode. after the power-up time from partial power-down has elapsed, the convstx signal should receive a rising edge to initiate a valid conversion. in partial power-down mode, the reference buffers remain powered up. while an adc pair is in partial power- down mode, conversions can still occur on the other adcs. the ad7656-1/ad7657-1/ad7658-1 have a standby mode whereby the devices can be placed into a low power consumption mode (100 w max). the ad7656-1/ad7657- 1/ad7658-1 are placed into standby mode by bringing the logic input stby low and can be powered up again for normal operation by bringing stby logic high. the output data buffers are still operational when the ad7656-1/ad7657-1/ad7658-1 are in standby mode, meaning the user can continue to access the conversion results of the parts. this standby feature can be used to reduce the average power consumed by the ad7656- 1/ad7657-1/ad7658-1 when operating at lower throughput rates. the parts can be placed into standby at the end of each conversion when busy goes low and taken out of standby again prior to the next conversion. the time for the ad7656- 1/ad7657-1/ad7658-1 to come out of standby is called the wake-up time. the wake-up time limits the maximum throughput rate at which the ad7656-1/ad7657-1/ad7658-1 can operate when powering down between conversions. see the specifications section.
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 28 of 32 digital host convert cs sclk ad7656-1/ ad7657-1/ ad7658-1 convst convst cs cs sclk sclk data in1 data in2 dout a dout b dout a dout b dcin a dcin b dcen = 1 device 1 dcen = 0 device 2 05020-013 ad7656-1/ ad7657-1/ ad7658-1 figure 33. daisy-ch ain configuration device 1, dout a msb v1 lsb v1 msb v2 lsb v2 msb v5 lsb v5 msb v1 lsb v1 msb v2 lsb v5 msb v1 lsb v1 msb v2 lsb v2 msb v5 lsb v5 123 busy sclk cs 15 16 17 31 32 33 47 48 49 63 65 64 94 95 96 device 1, dout b msb v3 lsb v3 msb v4 lsb v4 msb v6 lsb v6 msb v3 lsb v3 msb v4 lsb v6 device 2, dout a msb v3 lsb v3 msb v4 lsb v4 msb v6 lsb v6 device 2, dout b 05020-014 convst a, convst b, convst c figure 34. daisy-chain serial interface timing with two dout lines device 1, dout a msb v1 lsb v1 msb v2 lsb v2 msb v1 lsb v1 msb v2 lsb v2 msb v1 lsb v1 msb v2 lsb v2 123 busy sclk cs 15 16 17 31 32 33 47 48 49 63 64 device 2, dout a msb v3 lsb v3 msb v4 lsb v4 device 2, dout b device 1, dout b msb v3 lsb v3 msb v4 lsb v4 msb v3 lsb v3 msb v4 lsb v4 device 1, dout c msb v5 lsb v5 msb v6 lsb v6 msb v5 lsb v5 msb v6 lsb v6 msb v5 lsb v5 msb v6 lsb v6 device 2, dout c 05020-015 convst a, convst b, convst c figure 35. daisy-chain serial interface timing with three dout lines
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc | page 29 of 32 application hints layout the printed circuit board that houses the ad7656-1/ad7657- 1/ ad7658-1 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. at least one ground plane should be used. it could be common or split between the digital and analog sections. in the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably underneath the ad7656-1/ ad7657-1/ad7658-1, or at least as close as possible to each part. if the ad7656-1/ad7657-1/ad7658-1 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point, a star ground point, which should be established as close as possible to the ad7656-1/ad7657-1/ad7658-1. good connections should be made to the ground plane. avoid sharing one connection for multiple ground pins. individual vias or multiple vias to the ground plane should be used for each ground pin. avoid running digital lines under the devices because doing so couples noise onto the die. the analog ground plane should be allowed to run under the ad7656-1/ad7657-1/ad7658-1 to avoid noise coupling. fast-switching signals like convst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other to reduce the effect of feedthrough through the board. the power supply lines to the av cc , dv cc , v drive , v dd , and v ss pins on the ad7656-1/ad7657-1/ad7658-1 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good connections should be made between the ad7656-1/ad7657- 1/ad7658-1 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin. good decoupling is also important to lower the supply impedance presented to the ad7656-1/ad7657-1/ad7658-1 and to reduce the magnitude of the supply spikes. the decoupling capacitors should be placed close to, ideally right up against, these pins and their corresponding ground pins. additionally, low esr 1 f capacitors should be placed on each of the supply pins, refinout and each refcap pin. avoid sharing these capacitors between pins. use big vias to connect the capacitors to the power and ground planes. use wide, short traces between the via and the capacitor pad, or place the via adjacent to the capacitor pad to minimize parasitic inductances. recommended decoupling is outlined in figure 26.
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 30 of 32 outline dimensions compliant to jedec standards ms-026-bcd top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 10.00 bsc sq 12.00 bsc sq pin 1 1.60 max 0.75 0.60 0.45 view a 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 0 . 1 5 0 . 0 5 7 3.5 0 figure 36. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad7656-1bst ?40c to +85c 64-lead low prof ile quad flat package [lqfp] st-64-2 ad7656-1bst-500rl7 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7656-1bstz 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7656-1bstz-reel 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7656-1bstz-500rl7 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7656-1ystz 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7656-1ystz-reel 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 AD7656-1YSTZ-500RL7 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657-1bstz 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657-1bstz-reel 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657-1bstz-500rl7 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657-1ystz 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657-1ystz-reel 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7657-1ystz-500rl7 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658-1bstz 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658-1bstz-reel 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658-1bstz-500rl7 1 ?40c to +85c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658-1ystz 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658-1ystz-reel 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 ad7658-1ystz-500rl7 1 ?40c to +125c 64-lead low profile quad flat package [lqfp] st-64-2 1 z = pb-free part.
preliminary technical data ad7656-1/ad7657-1/ad7658-1 rev. prc | page 31 of 32 notes
ad7656-1/ad7657-1/ad7658-1 preliminary technical data rev. prc| page 32 of 32 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr07017-0-8/06(prc)

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